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FPGAs, FPSCs, CPLDs and SPLDs:
LatticeECP3
LatticeECP2/M
LatticeEC/ECP
LatticeSC
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MachXO
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FPSC and ORCA Series 4
CPLDs and SPLDs
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ispClock
Platform & Power Manager
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Design Tools and IP:
Lattice Diamond
ispLEVER
ispLEVER Classic
IP and Reference Designs
LatticeMico32
Lattice Diamond Known Issues
1.0
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1.1
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1.2
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1.3
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1.4
ispLEVER Known Issues
6.0
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6.1
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6.1 SP1
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6.1 SP2
7.0
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7.0 SP1
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7.0 SP2
|
7.1
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7.1 SP1
7.2
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7.2 SP1
|
7.2 SP2
8.0
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8.0 SP1
8.1
|
8.1SP1
Other design tools
(ispVM, ispPAC, eval boards etc)
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Recent Threads
Open Drain Pins can be Input I/O?
MachXO2 in QFN packages ? When ?
Timing-parameters EBR-FIFO_DC in MACHXO2
FLEXlm error
ECP3 EBR clock information
LSE vs Synplify Pro Code Error Difference: Which is correct?
BKM warning - Sensitivity List
SPI Slave